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CS4245
105 dB, 24-Bit, 192 kHz Stereo Audio CODEC
D/A Features
Multi-bit Delta Sigma modulator 105 dB dynamic range -95 dB THD+N Up to 192 kHz sampling rates Single-ended analog architecture Volume control with soft ramp
- 0.5 dB step size - Zero crossing click-free transitions
A/D Features
Multi-bit Delta Sigma modulator 105 dB dynamic range -95 dB THD+N Stereo 6:1 Input Multiplexer Programmable Gain Amplifier (PGA)
- +/- 12 dB gain, 0.5 dB step size - Zero crossing, click-free transitions
Stereo microphone inputs
- +32 dB gain stage - Low noise bias supply
PopguardTM
Technology
- Minimizes the effects of output transients
Filtered line level outputs Selectable serial audio interface formats
- Left justified up to 24-bit - IS up to 24-bit - Right justified 16, 18, 20 and 24-bit
Up to 192 kHz sampling rates Selectable serial audio interface formats
- Left justified up to 24-bit - IS up to 24-bit
High pass filter or DC offset calibration
Selectable 50/15 s de-emphasis Control Output for External Muting
1.8 V to 5 V
3.3 V to 5 V
3.3 V to 5 V
PCM Serial Interface
Level Translator
Serial Audio Input I2C/SPI Control Data Interrupt ADC Overflow Reset
Volume Control Volume Control
Interpolation Filter Interpolation Filter
Multibit Modulator Multibit Modulator
Switched Capacitor DAC and Filter
Left DAC Output Mute Control Mute Control Right DAC Output MUX Left Aux Output Right Aux Output Stereo Input 1 Stereo Input 2 Stereo Input 3
Switched Capacitor DAC and Filter
Level Translator
Register Configuration PCM Serial Interface
Internal Voltage Reference
Serial Audio Output
Level Translator
High Pass Filter
Linear Phase Anti-Alias Filter
Multibit Oversampling ADC Multibit Oversampling ADC
PGA MUX PGA
+32 dB
Stereo Input 4 / Mic Input 1 & 2
+32 dB
High Pass Filter
Linear Phase Anti-Alias Filter
Stereo Input 5 Stereo Input 6
Preliminary Product Information
Cirrus Logic, Inc. www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2004 (All Rights Reserved)
(c)
AUG `04 DS656PP1 1
CS4245
System Features
Direct interface with 1.8 V to 5 V logic levels Optional asynchronous serial port operation
- Each serial port supports master or slave operation
General Description
The CS4245 is a highly integrated stereo audio CODEC. The CS4245 performs stereo analog-to-digital (A/D) and digital-to-analog (D/A) conversion of up to 24-bit serial values at sample rates up to 192 kHz. A 6:1 stereo input multiplexer is included for selecting between line level or microphone level inputs. The microphone input path includes a +32 dB gain stage and a low noise bias voltage supply. The PGA is available for line or microphone inputs and provides gain/attenuation of 12 dB in 0.5 dB steps. The output of the PGA is followed by an advanced 5thorder, multi-bit delta sigma modulator and digital filtering/decimation. Sampled data is transmitted by the serial audio interface at rates from 4 kHz to 192 kHz in either slave or master mode. The D/A converter is based on a 4th-order multi-bit delta sigma modulator with an ultra-linear low pass filter and offers a volume control that operates with a 0.5 dB step size. It incorporates selectable soft ramp and zero crossing transition functions to eliminate clicks and pops. Standard 50/15 s de-emphasis is available for a 44.1 kHz sample rate for compatibility with digital audio programs mastered using the 50/15 s pre-emphasis technique. Integrated level translators allow easy interfacing between the CS4245 and other devices operating over a wide range of logic levels.
Selectable auxiliary analog output
- Allows analog monitoring of either the ADC input signal after PGA or DAC output signal
Internal digital loopback Power down mode
- Available for A/D, D/A, CODEC, Mic Preamplifier
+3.3 V to +5 V analog power supply +3.3 V to +5 V digital power supply Supports IC and SPI control port interfaces Pin-compatible with CS5345
ORDERING INFORMATION CS4245-CQZ -10 to 70 C CDB4245
48-pin LQFP Evaluation Board
2
CS4245
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................... 5 2. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 8 SPECIFIED OPERATING CONDITIONS ................................................................................. 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 8 DAC ANALOG CHARACTERISTICS ....................................................................................... 9 DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE................ 10 ADC ANALOG CHARACTERISTICS ..................................................................................... 12 ADC ANALOG CHARACTERISTICS ..................................................................................... 14 ADC DIGITAL FILTER CHARACTERISTICS......................................................................... 15 AUXILIARY OUTPUT ANALOG CHARACTERISTICS .......................................................... 16 AUXILIARY OUTPUT ANALOG CHARACTERISTICS (CONT'D) ......................................... 17 AUXILIARY OUTPUT ANALOG CHARACTERISTICS (CONT'D) ......................................... 18 DC ELECTRICAL CHARACTERISTICS ................................................................................ 19 DIGITAL INTERFACE CHARACTERISTICS ......................................................................... 20 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1.............................................. 21 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2.............................................. 23 SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT ................................ 26 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ............................... 27 3. TYPICAL CONNECTION DIAGRAM .................................................................................... 28 4. APPLICATIONS .................................................................................................................... 29 4.1 Recommended Power-Up Sequence ............................................................................. 29 4.2 System Clocking ............................................................................................................. 29 4.2.1 Synchronous / Asynchronous Mode .................................................................. 29 4.2.2 Master Clock ...................................................................................................... 29 4.2.3 Master Mode ...................................................................................................... 30 4.2.4 Slave Mode ........................................................................................................ 30 4.3 High Pass Filter and DC Offset Calibration .................................................................... 31 4.4 Analog Input Multiplexer, PGA, and Mic Gain ................................................................ 31 4.5 Input Connections ........................................................................................................... 32 4.6 Output Connections ........................................................................................................ 32 4.7 Output Transient Control ................................................................................................ 32 4.7.1 Power-up ............................................................................................................ 32 4.7.2 Power-down ....................................................................................................... 32 4.7.3 Serial Interface Clock Changes ......................................................................... 32 4.8 Auxiliary Analog Output .................................................................................................. 32 4.9 De-Emphasis Filter ......................................................................................................... 33 4.10 Internal Digital Loopback .............................................................................................. 33 4.11 Mute Control ................................................................................................................. 33 4.12 Control Port Description and Timing ............................................................................. 34 4.12.1 SPI Mode ......................................................................................................... 34 4.12.2 IC Mode .......................................................................................................... 35 4.13 Interrupts and Overflow ................................................................................................ 37 4.14 Reset ........................................................................................................................... 37 4.15 Synchronization of Multiple Devices ............................................................................. 37 4.16 Grounding and Power Supply Decoupling .................................................................... 37 5. REGISTER QUICK REFERENCE ......................................................................................... 38 6. REGISTER DESCRIPTION ................................................................................................... 39 6.1 Chip ID - Register 01h .................................................................................................... 39 6.2 Power Control - Address 02h ......................................................................................... 39 6.3 DAC Control - Address 03h ............................................................................................ 40 6.4 ADC Control - Address 04h ............................................................................................ 41 6.5 MCLK Frequency - Address 05h .................................................................................... 42 3
CS4245
6.6 Signal Selection - Address 06h ....................................................................................... 43 6.7 Channel A PGA Control - Address 07h ........................................................................... 43 6.8 Channel B PGA Control - Address 08h ........................................................................... 44 6.9 ADC Input Control - Address 09h ................................................................................... 44 6.10 DAC Channel A Volume Control - Address 0Ah ........................................................... 45 6.11 DAC Channel B Volume Control - Address 0Bh ........................................................... 45 6.12 DAC Control 2 - Address 0Ch ....................................................................................... 46 6.13 Interrupt Status - Address 0Dh ..................................................................................... 46 6.14 Interrupt Mask - Address 0Eh ....................................................................................... 47 6.15 Interrupt Mode MSB - Address 0Fh .............................................................................. 47 6.16 Interrupt Mode LSB - Address 10h ............................................................................... 47 7. PARAMETER DEFINITIONS ................................................................................................. 48 8. PACKAGE DIMENSIONS ...................................................................................................... 49 9. THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................. 49 Appendix A: DAC Filter Plots ......................................................................................... 50 Appendix B: ADC Filter Plots .............................................................................................. 52
4
CS4245
1. PIN DESCRIPTIONS
SDOUT
MCLK1
MCLK2
LRCK1
LRCK2
SCLK1
SCLK2
DGND
OVFL
48 47 46 45 44 43 42 41 40 39 38 37
SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RESET AIN3A AIN3B AIN2A AIN2B AIN1A AIN1B
SDIN
INT
VD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
AIN4A/MICIN1 AIN4B/MICIN2 VQ1 VQ2 FILT1+ AFILTA AFILTB FILT2+ AIN5A AGND AIN5B VA
36 35 34 33 32
VLS MUTEC AOUTB AOUTA AGND AGND VA AUXOUTB AUXOUTA AIN6B AIN6A MICBIAS
CS4245
31 30 29 28 27 26 25
Pin Name
SDA/CDOUT SCL/CCLK AD0/CS AD1/CDIN VLC RESET AIN3A AIN3B
# 1 2 3 4 5 6 7, 8
Pin Description
Serial Control Data (Input/Output) - SDA is a data I/O in IC mode. CDOUT is the output data line for the control port interface in SPI mode. Serial Control Port Clock (Input) - Serial clock for the serial control port. Address Bit 0 (IC) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in IC mode; CS is the chip select signal for SPI format. Address Bit 1 (IC) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in IC mode; CDIN is the input data line for the control port interface in SPI mode. Control Port Power (Input) - Determines the required signal level for the control port interface. Refer to the Recommended Operating Conditions for appropriate voltages. Reset (Input) - The device enters a low power mode when this pin is driven low. Stereo Analog Input 3 (Input) - The full scale level is specified in the ADC Analog Characteristics specification table.
5
CS4245
AIN2A AIN2B AIN1A AIN1B AGND VA AFILTA AFILTB VQ1 VQ2 FILT1+ FILT2+ AIN4A/MICIN1 AIN4B/MICIN2 AIN5A AIN5B MICBIAS AIN6A AIN6B AUXOUTA AUXOUTB VA AGND AOUTA AOUTB MUTEC VLS SDIN SCLK2 LRCK2 MCLK2 SDOUT SCLK1 LRCK1
9, 10
Stereo Analog Input 2 (Input) - The full scale level is specified in the ADC Analog Characteristics specification table.
11, Stereo Analog Input 1 (Input) - The full scale level is specified in the ADC Analog Characteristics 12 specification table. 13 14 15 16 17 18 19 20
Analog Ground (Input) - Ground reference for the internal analog section. Analog Power (Input) - Positive power for the internal analog section. Antialias Filter Connection (Output) - Antialias filter connection for the channel A ADC input. Antialias Filter Connection (Output) - Antialias filter connection for the channel B ADC input. Quiescent Voltage 1 (Output) - Filter connection for the internal quiescent reference voltage. Quiescent Voltage 2 (Output) - Filter connection for the internal quiescent reference voltage. Positive Voltage Reference 1 (Output) - Positive reference voltage for the internal sampling circuits. Positive Voltage Reference 2 (Output) - Positive reference voltage for the internal sampling circuits.
21, Stereo Analog Input 4 / Microphone Input 1 & 2 (Input) - The full scale level is specified in the ADC 22 Analog Characteristics specification table. 23, Stereo Analog Input 5 (Input) - The full scale level is specified in the ADC Analog Characteristics 24 specification table. 25
Microphone Bias Supply (Output) - Low noise bias supply for external microphone. Electrical characteristics are specified in the DC Electrical Characteristics specification table.
26, Stereo Analog Input 6 (Input) - The full scale level is specified in the ADC Analog Characteristics 27 specification table. 28, Auxiliary Analog Audio Output (Output) - Analog output from either the DAC, the PGA block, or high 29 impedance. See "Auxiliary Output Source Select (Bits 6:5)" on page 43. 30
Analog Power (Input) - Positive power for the internal analog section.
31, Analog Ground (Input) - Ground reference for the internal analog section. 32 33, DAC Analog Audio Output (Output) - The full scale output level is specified in the DAC Analog Char34 acteristics specification table. 35 36 37 38 39 40 41 42 43
Mute Control (Output) - This pin is active during power-up initialization, reset, muting, when master clock to left/right clock frequency ratio is incorrect, or power-down. Serial Audio Interface Power (Input) - Determines the required signal level for the serial audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. Serial Audio Data Input (Input) - Input for two's complement serial audio data. Serial Port 2 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 2. Serial Port 2 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio input data line. Master Clock 2 (Input/Output) -Optional asynchronous clock source for the DAC's delta-sigma modulators. Serial Audio Data Output (Output) - Output for two's complement serial audio data. Serial Port 1 Serial Bit Clock (Input/Output) - Serial bit clock for serial audio interface 1. Serial Port 1 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the serial audio output data line.
6
CS4245
MCLK1 DGND VD INT OVFL
44 45 46 47 48
Master Clock 1 (Input/Output) -Clock source for the ADC's delta-sigma modulators. By default, this signal also clocks the DAC's delta-sigma modulators. Digital Ground (Input) - Ground reference for the internal digital section. Digital Power (Input) - Positive power for the internal digital section. Interrupt (Output) - Indicates an interrupt condition has occurred. ADC Overflow (Output) - Indicates an ADC overflow condition is present.
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CS4245
2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25C.)
SPECIFIED OPERATING CONDITIONS (AGND = DGND = 0 V; All voltages with respect to
ground.) Parameters Analog Digital Logic - Serial Port Logic - Control Port Ambient Operating Temperature (Power Applied) DC Power Supplies: Symbol VA VD VLS VLC TA Min 3.1 3.1 1.71 1.71 -10 Nom 5.0 3.3 3.3 3.3 Max 5.25 5.25 5.25 5.25 +70 Units V V V V C
ABSOLUTE MAXIMUM RATINGS (AGND = DGND = 0 V All voltages with respect to ground.) (Note
1) Parameter DC Power Supplies: Analog Digital Logic - Serial Port Logic - Control Port (Note 2) Symbol VA VD VLS VLC Iin VINA Logic - Serial Port VIND-S Logic - Control Port VIND-C TA Tstg Min -0.3 -0.3 -0.3 -0.3 AGND-0.3 -0.3 -0.3 -20 -65 Typ Max +6.0 +6.0 +6.0 +6.0 10 VA+0.3 VLS+0.3 VLC+0.3 +85 +150 Units V V V V mA V V V C C
Input Current Analog Input Voltage Digital Input Voltage
Ambient Operating Temperature (Power Applied) Storage Temperature
Notes: 1. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up.
8
CS4245
DAC ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load RL = 3 k,
CL = 10 pF (see Figure 1), Fs = 48/96/192 kHz. Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.) Synchronous mode. All Speed Modes Parameter Dynamic Performance for VA = 5 V Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit (Note 3) unweighted A-Weighted unweighted A-Weighted (Note 3) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (Note 3) unweighted A-Weighted unweighted A-Weighted (Note 3) THD+N 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB (1 kHz) Symbol Min Typ Max Unit
96 99 87 90 -
102 105 93 96 -95 -82 -42 -93 -73 -33
-89 -76 -36 -87 -67 -27
dB dB dB dB dB dB dB dB dB dB
16-Bit
Dynamic Performance for VA = 3.3 V Dynamic Range 18 to 24-Bit
16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit
93 96 85 88 0.60*VA
99 102 90 93 -92 -79 -39 -90 -70 -30 100 0.1 100 0.65*VA 100
-84 -71 -31 -82 -62 -22 0.25 0.70*VA 10 100 -
dB dB dB dB dB dB dB dB dB dB dB dB ppm/C Vpp A k pF
16-Bit
Interchannel Isolation
DC Accuracy Interchannel Gain Mismatch
Gain Drift
Analog Output
Full Scale Output Voltage DC Current draw from an AOUT pin AC-Load Resistance Load Capacitance Output Impedance Note: (Note 4) (Note 5) (Note 5) IOUT RL CL ZOUT 3 -
3. One-half LSB of triangular PDF dither added to data. 4. Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pin due to typical leakage through the electrolytic DC blocking capacitors. 5. Guaranteed by design. See Figure 2. R L and C L reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability. CL affects the dominant pole of the internal output amp; increasing CL beyond 100 pF can cause the internal op-amp to become unstable. 9
CS4245
DAC COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter (Note 6,9) Combined Digital and On-chip Analog Filter Response Passband (Note 6) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 8) Fs = 44.1 kHz (Note 7) tgd to -0.05 dB corner to -3 dB corner Symbol Min 0 0 -.01 .5465 50 Typ Single Speed Mode 10/Fs Max .4780 .4996 +.08 +.05/-.25 Unit Fs Fs dB Fs dB s dB Fs Fs dB Fs dB s Fs Fs dB Fs dB s
Combined Digital and On-chip Analog Filter Response Passband (Note 6) to -0.1 dB corner to -3 dB corner
Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay (Note 7) tgd
Double Speed Mode 0 .4650 0 .4982
-.05 .5770 55 5/Fs +.2 0.397 0.476 +0.00004 -
Combined Digital and On-chip Analog Filter Response Passband (Note 6) to -0.1 dB corner to -3 dB corner
Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay Notes: 6. Filter response is guaranteed by design. (Note 7) tgd
Quad Speed Mode 0 0 0 0.7 51 2.5/Fs
7. For Single Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs. 8. De-emphasis is available only in Single Speed Mode. 9. Response is clock dependent and will scale with Fs. Note that the amplitude vs. frequency plots of this data (Figures 21 to 30) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
10
CS4245
125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region
3.3 F AOUTx R C V out L L
AGND
2.5 3
5
10
15
20
Resistive Load -- RL (k )
Figure 1. DAC Output Test Load
Figure 2. Maximum DAC Loading
11
CS4245
ADC ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. Fs = 48/96/192 kHz. Synchronous mode. Line Level Inputs Parameter Dynamic Performance for VA = 5 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted (Note 12) 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted (Note 12) 40 kHz bandwidth unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Symbol Min Typ Max Unit
99 96 -
105 102 99
-
dB dB dB
93 90 THD+N
99 96 93
-
dB dB dB
(Note 12)
-
-95 -82 -42 -92
-89 -
dB dB dB dB
PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB (Note 12) 40 kHz bandwidth -1 dB Dynamic Performance for VA = 3.3 V Dynamic Range PGA Setting: -12 dB to +6 dB A-weighted unweighted (Note 12) 40 kHz bandwidth unweighted PGA Setting: +12 dB Gain A-weighted unweighted 40 kHz bandwidth unweighted
-
-92 -76 -36 -89
-86 -
dB dB dB dB
94 91 -
102 99 96
-
dB dB dB
(Note 12)
90 87 -
96 93 90
-
dB dB dB
12
CS4245
Total Harmonic Distortion + Noise (Note 11) THD+N
(Note 12)
PGA Setting: -12 dB to +6 dB -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB PGA Setting: +12 dB Gain -1 dB -20 dB -60 dB 40 kHz bandwidth -1 dB Line Level Inputs Symbol
-
-92 -79 -39 -84
-86 -
dB dB dB dB
(Note 12)
Min 0.53*VA 6.12 -
-89 -73 -33 -81 Typ 90 0.56*VA 6.8 5
-83 Max 0.59*VA 7.48 -
dB dB dB dB Unit dB Vpp k %
Parameter Interchannel Isolation Line Level Input Characteristics Full-scale Input Voltage Input Impedance (Note 10) Maximum Interchannel Input Impedance Mismatch
Line Level and Microphone Level Inputs Parameter DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Programmable Gain Characteristics Gain Step Size Absolute Gain Step Error 10. Valid for the selected input pair. Symbol Min Typ 0.1 Max Unit dB % ppm/C dB dB
100
0.5 -
5
0.4
13
CS4245
ADC ANALOG CHARACTERISTICS
Parameter Dynamic Performance for VA = 5 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB -1 dB Dynamic Performance for VA = 3.3 V Dynamic Range PGA Setting: -12 dB to 0 dB A-weighted unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 11) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB PGA Setting: +12 dB -1 dB Interchannel Isolation Microphone Level Input Characteristics Full-scale Input Voltage Input Impedance (Note 13) (cont)
Microphone Level Inputs Symbol Min Typ Max Unit
77 74
83 80
-
dB dB
65 62 THD+N
71 68
-
dB dB
-
-80 -60 -20
-74 -
dB dB dB
-
-68
-
dB
77 74
83 80
-
dB dB
65 62 THD+N
71 68
-
dB dB
-
-80 -60 -20
-74 -
dB dB dB
0.013*VA -
-68 30 0.014*VA 100
0.015*VA -
dB dB Vpp k
11. Referred to the typical line level full-scale input voltage 12. Valid for Double and Quad Speed Modes only. 13. Valid when the microphone level inputs are selected.
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CS4245
ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 14, 16) Symbol Min 0 0.5688 70 tgd 0 0.5604 69 tgd 0 0.5000 60 tgd (Note 15) (Note 15) Typ 12/Fs 9/Fs 5/Fs 1 20 10 10 /Fs
5
Max 0.4896 0.035 0.4896 0.025 0.2604 0.025 0
Unit Fs dB Fs dB s Fs dB Fs dB s Fs dB Fs dB s Hz Hz Deg dB s
Single Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB)
Double Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB)
Quad Speed Mode
Passband Passband Ripple Stopband Stopband Attenuation Total Group Delay (Fs = Output Sample Rate) (-0.1 dB)
High Pass Filter Characteristics
Frequency Response Phase Deviation Passband Ripple Filter Settling Time Note: 14. Filter response is guaranteed by design. 15. Response shown is for Fs equal to 48 kHz. 16. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 33 to 44) are normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. -3.0 dB -0.13 dB @ 20Hz
15
CS4245
AUXILIARY OUTPUT ANALOG CHARACTERISTICS
Test conditions (unless otherwise specified): Synchronous mode, Fs = 48/96/192 kHz. Input test signal is a 1 kHz sine wave; measurement bandwidth is 10 Hz to 20 kHz. VA = 5 V Parameter Symbol Min Dynamic Performance with PGA Output Selected, Line Level Input Dynamic Range (Note 18) PGA Setting: -12 dB to +6 dB 99 A-weighted 96 unweighted PGA Setting: +12 dB Gain 93 A-weighted 90 unweighted Total Harmonic Distortion + Noise (Note 18) THD+N PGA Setting: -12 dB to +12 dB -1 dB -20 dB -60 dB Dynamic Performance with PGA Output Selected, Mic Level Input Dynamic Range (Note 18) PGA Setting: -12 dB to 0 dB 77 A-weighted 74 unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 18) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB Typ Max Unit
105 102
-
dB dB
99 96
-
dB dB
-80 -82 -42
-74 -
dB dB dB
83 80
-
dB dB
65 62 THD+N -
71 68
-
dB dB
-74 -60 -20
-68 -
dB dB dB
PGA Setting: +12 dB -1 dB Dynamic Performance with DAC Output Selected Dynamic Range (Notes 17, 18) 18 to 24-Bit A-Weighted unweighted 16-Bit A-Weighted unweighted Total Harmonic Distortion + Noise (Notes 17, 18) THD+N 16 to 24-Bit 0 dB -20 dB -60 dB
-
-68
-
dB
99 96 90 87 -
105 102 96 93 -80 -82 -42
-74 -
dB dB dB dB dB dB dB
16
CS4245
AUXILIARY OUTPUT ANALOG CHARACTERISTICS (CONT'D)
VA = 3.3 V Parameter Symbol Min Dynamic Performance with PGA Output Selected, Line Level Input Dynamic Range (Note 18) PGA Setting: -12 dB to +6 dB 94 A-weighted 91 unweighted PGA Setting: +12 dB Gain 90 A-weighted 87 unweighted Total Harmonic Distortion + Noise (Note 18) THD+N PGA Setting: -12 dB to +12 dB -1 dB -20 dB -60 dB Dynamic Performance with PGA Output Selected, Mic Level Input Dynamic Range (Note 18) PGA Setting: -12 dB to 0 dB 77 A-weighted 74 unweighted PGA Setting: +12 dB A-weighted unweighted Total Harmonic Distortion + Noise (Note 18) PGA Setting: -12 dB to 0 dB -1 dB -20 dB -60 dB Typ Max Unit
102 99
-
dB dB
96 93
-
dB dB
-80 -82 -42
-74 -
dB dB dB
83 80
-
dB dB
65 62 THD+N -
71 68
-
dB dB
-74 -60 -20
-68 -
dB dB dB
PGA Setting: +12 dB -1 dB Dynamic Performance with DAC Output Selected Dynamic Range (Notes 17, 18) 18 to 24-Bit A-Weighted unweighted 16-Bit A-Weighted unweighted Total Harmonic Distortion + Noise (Notes 17, 18) THD+N 16 to 24-Bit 0 dB -20 dB -60 dB Notes: 17. One-half LSB of triangular PDF dither added to data.
-
-68
-
dB
96 93 88 85 -
102 99 93 90 -80 -82 -42
-74 -
dB dB dB dB dB dB dB
18. Referred to the typical AUXOUT Full-Scale Output Voltage.
17
CS4245
AUXILIARY OUTPUT ANALOG CHARACTERISTICS (CONT'D)
VA = 5 V or 3.3 V Parameter DC Accuracy Interchannel Gain Mismatch Gain Error Gain Drift Analog Output Full-Scale Output Voltage PGA Output Selected DAC Output Selected Frequency Response 10 Hz to 20 kHz Analog In to Analog Out Phase Shift (Note 19) DC Current draw from an AUXOUT pin AC-Load Resistance Load Capacitance Output Impedance Notes: 19. Valid only when PGA output is selected. Symbol Min Typ 0.1 Max Unit dB % ppm/C
5 100
0.56*VA 0.7*VA 180 1
IOUT RL CL ZOUT
-0.1dB 100 -
VA 0.75*VA +0.1dB 1 20 -
Vpp Vpp dB deg A k pF k
18
CS4245
DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V, all voltages with respect to
ground. MCLK=12.288 MHz; Fs=48 kHz, Master Mode) Parameter Power Supply Current (Normal Operation) VA = 5 VA = 3.3 VD, VLS, VLC = 5 VD, VLS, VLC = 3.3 V V V V Symbol IA IA ID ID IA ID PSRR VQ1 (Note 22) IQ1 ZQ1 VQ2 (Note 22) IQ2 ZQ2 FILT1+ FILT2+ MICBIAS IMB Min Typ 41 37 39 23 0.50 0.54 400 198 4.2 60 0.5 x VA 23 0.5 x VA 23 VA VA 0.8 x VA Max 50 45 47 28 485 241 1 1 2 Unit mA mA mA mA mA mA mW mW mW dB VDC A k VDC A k VDC VDC VDC mA
Power Supply Current. (Power-Down Mode) (Note 20). Power Consumption (Normal Operation). (Power-Down Mode). VQ Characteristics Quiescent Voltage 1 DC Current from VQ1 VQ1 Output Impedance Quiescent Voltage 2 DC Current from VQ2 VQ2 Output Impedance FILT1+ Nominal Voltage FILT2+ Nominal Voltage Microphone Bias Voltage Current from MICBIAS
VA = 5 V VLS, VLC, VD=5 V
VA, VD, VLS, VLC = 5 V VA, VD, VLS, VLC = 3.3 V VA, VD, VLS, VLC = 5 V (1 kHz) (Note 21)
Power Supply Rejection Ratio
Notes: 20. Power Down Mode is defines as RESET = Low with all clock and data lines held static and no analog input. 21. Valid with the recommended capacitor values on FILT1+, FILT2+, VQ1 and VQ2 as shown in the Typical Connection Diagram. 22. Guaranteed by design. The DC current draw represents the allowed current draw due to typical leakage through the electrolytic de-coupling capacitors.
19
CS4245
DIGITAL INTERFACE CHARACTERISTICS
Parameters (Note 23) High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage at Io=2 mA Symbol VIH Serial Port VIH Control Port VIL Serial Port VIL Control Port Serial Port VOH Control Port VOH MUTEC VOH Serial Port Control Port MUTEC VOL VOL VOL Iin (Note 24) Min 0.7xVLS 0.7xVLC VLS-1.0 VLC-1.0 VA-1.0 10 ------------------LRCK1
6
Typ 3
Max 0.2xVLS 0.2xVLC 0.4 0.4 0.4 10 1 -
Units V V V V V V V V V V A pF mA s
Low-Level Output Voltage at Io=2 mA
Input Leakage Current Input Capacitance Maximum MUTEC Drive Current Minimum OVFL Active Time
Notes: 23. Serial Port signals include: MCLK1, MCLK2, SCLK1, SCLK2, LRCK1, LRCK2, SDIN, SDOUT. Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, RESET, INT, OVFL. 24. Guaranteed by design.
20
CS4245
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 1 (Logic `0' = DGND = 0 V;
Logic `1' = VL, CL = 20 pF) (Note 25) Parameter Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs fmclk tclkhl Min 4 50 100 1.024 8 tslr tsdo -10 0 40 Single Speed Mode Double Speed Mode Quad Speed Mode SCLK1 Pulse Width High SCLK1 Pulse Width Low SCLK1 falling to LRCK1 edge SCLK1 falling to SDOUT valid 25. See figures 3 and 4 on page 22. tsclkw tsclkw tsclkw tsclkh tsclkl tslr tsdo
10 -------------------( 128 )Fs 10 ----------------( 64 )Fs 10 ----------------( 64 )Fs
9 9 9
Typ 50 50 50 -
Max 50 100 200 51.200 10 32 60 10 32
Unit kHz kHz kHz MHz ns % % ns ns % ns ns ns ns ns ns ns
MCLK Specifications MCLK1 Input Frequency
MCLK1 Input Pulse Width High/Low
Master Mode
LRCK1 Duty Cycle SCLK1 Duty Cycle SCLK1 falling to LRCK1 edge SCLK1 falling to SDOUT valid
Slave Mode LRCK1 Duty Cycle
SCLK1 Period
30 48 -10 0
21
CS4245
LRCK1 Output
t SCLK1 Output t SDOUT
slr
sdo
Figure 3. Master Mode Timing - Serial Audio Port 1
LRCK1 Input t sclkh t
t SCLK1 Input t SDOUT
slr
sclkl
sdo
t sclkw
Figure 4. Slave Mode Timing - Serial Audio Port 1
22
CS4245
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT 2 (Logic `0' = DGND = 0 V;
Logic `1' = VL, CL = 20 pF) (Note 26) Parameter Sample Rate Single Speed Mode Double Speed Mode Quad Speed Mode Symbol Fs Fs Fs fmclk tclkhl Min 4 50 100 1.024 8 tslr tsdis tsdih -10 16 20 40 Single Speed Mode Double Speed Mode Quad Speed Mode SCLK2 Pulse Width High SCLK2 Pulse Width Low SCLK2 falling to LRCK2 edge SDIN valid to SCLK2 rising setup time SCLK2 rising to SDIN hold time 26. See figures 5 and 6 on page 24. tsclkw tsclkw tsclkw tsclkh tsclkl tslr tsdis tsdih
10 -------------------( 128 )Fs 10 ----------------( 64 )Fs 10 ----------------( 64 )Fs
9 9 9
Typ 50 50 50 -
Max 50 100 200 51.200 10 60 10 -
Unit kHz kHz kHz MHz ns % % ns ns ns % ns ns ns ns ns ns ns ns
MCLK Specifications MCLK2 Input Frequency
MCLK2 Input Pulse Width High/Low
Master Mode
LRCK2 Duty Cycle SCLK2 Duty Cycle SCLK2 falling to LRCK edge SDIN valid to SCLK2 rising setup time SCLK2 rising to SDIN hold time
Slave Mode
LRCK2 Duty Cycle SCLK2 Period
30 48 -10 16 20
23
CS4245
LRCK2 Output
t SCLK2 Output
slr
t SDIN
sdis
t
sdih
Figure 5. Master Mode Timing - Serial Audio Port 2
LRCK2 Input t sclkh t
t SCLK2 Input
slr
sclkl
t sclkw t SDIN sdis t sdih
Figure 6. Slave Mode Timing - Serial Audio Port 2
24
CS4245
LRCK SCLK
Left Channel Channel A - Left
Channel B - Right Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 7. Format 0, Left Justified up to 24-Bit Data
LRCK SCLK
Channel A - Left Left Channel
Channel B - Right Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Figure 8. Format 1, IS up to 24-Bit Data
LRCK
Channel A - Left Left Channel
Channel B - Right Right Channel
SCLK
SDATA
LS B
M B-1 -2 -3 -4 -5 -6 S
B +6 +5 +4 +3 +2 +1 LS
M B -1 -2 -3 -4 -5 -6 S
B +6 +5 +4 +3 +2 +1 LS
32 clocks
Figure 9. Format 2, Right Justified 16-Bit Data. Format 3, Right Justified 24-Bit Data.
25
CS4245
SWITCHING CHARACTERISTICS - CONTROL PORT - IC FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF) Parameter SCL Clock Frequency RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling (Note 28) (Note 28) (Note 27) Symbol fscl tirs tbuf thdst tlow thigh tsust thdd tsud trc tfc tsusp tack Min 500 4.7 4.0 4.7 4.0 4.7 0 250 4.7 300 Max 100 1 300 1000 Unit kHz ns s s s s s s ns s ns s ns
Notes: 27. Data must be held for sufficient time to bridge the transition time, tfc, of SCL. 28. Guaranteed by design.
RST t Stop irs S tart R ep e a te d Sta rt t rd t fd Stop
S DA t buf t hdst t high t hdst t fc t susp
SCL t t t t t sust t rc
lo w
hdd
sud
ack
Figure 10. Control Port Timing - IC Format
26
CS4245
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT
(Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF) Parameter CCLK Clock Frequency RESET Rising Edge to CS Falling. CS High Time Between Transmissions CS Falling to CCLK Edge CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time CCLK Falling to CDOUT Stable Rise Time of CDOUT Fall Time of CDOUT Rise Time of CCLK and CDIN Fall Time of CCLK and CDIN (Note 30) (Note 30) (Note 29) Symbol fsck tsrs tcsh tcss tscl tsch tdsu tdh tpd tr1 tf1 tr2 tf2 Min 0 500 1.0 20 66 66 40 15 Typ Max 6.0 ns 50 25 25 100 100 s ns ns ns ns ns ns ns ns ns ns Units MHz
Notes: 29. Data must be held for sufficient time to bridge the transition time of CCLK. 30. For fsck <1 MHz.
RST
t srs
CS t css CCLK t r2 CDIN t dsu t dh t f2 t scl t sch t csh
t pd
CDOUT
Figure 11. Control Port Timing - SPI Format
27
CS4245
3. TYPICAL CONNECTION DIAGRAM
+3.3V to +5V 10 F 0.1 F 0.1 F 0.1 F 10 F +3.3V to +5V
VD +1.8V to +5V 0.1 F VLS
VA
VA
3.3 F
AUXOUTA
3.3 F
MCLK2 Digital Audio Playback SCLK2 LRCK2 SDIN
AUXOUTB MUTEC
3.3 F Mute Drive 470 10 k
See Note 2
AOUTA
* *
C C
MCLK1
10 k
Optional Analog Muting
Rext Rext
Digital Audio Capture
SCLK1 LRCK1 SDOUT
AOUTB
3.3 F 470
AIN1A
1800 pF *
10 F 100
Left Analog Input 1
100 k 100 k
INT OVFL RESET MicroController SCL/CCLK SDA/CDOUT AD1/CDIN AD0/CS 2 k +1.8V to +5V
See Note 1
AIN1B AIN2A
1800 pF
*
10 F
100
Right Analog Input 1 Left Analog Input 2
100 k 100 k
1800 pF *
10 F 100
AIN2B AIN3A
1800 pF
*
10 F
100
Right Analog Input 2 Left Analog Input 3
100 k 100 k
2 k VLC 0.1 F AIN3B AIN4A/MICIN1
1800 pF *
10 F 100
1800 pF
*
10 F
100
Right Analog Input 3 Left Analog Input 4
100 k 100 k
Note 1: Resistors are required for IC control port operation Note 2 : For best response to Fs/2 :
1800 pF *
10 F 100
AIN4B/MICIN2
C= Rext + 470 4Fs (Rext x 470)
1800 pF
*
10 F
100
Right Analog Input 4 Left Analog Input 5
100 k 100 k
AIN5A
1800 pF *
10 F 100
This circuitry is intended for applications where the CS4245 connects directly to an unbalanced output of the design. For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations.
AIN5B AIN6A VQ1 FILT1+
1800 pF
*
10 F
100
Right Analog Input 5 Left Analog Input 6
100 k 100 k
1800 pF *
10 F 100
10 F 0.1 F
47 F 47 F
0.1 F AGND 0.1 F FILT2+ VQ2 DGND
AIN6B MICBIAS AGND AGND AFILTA AFILTB
1800 pF
*
10 F
100 Note 3
Right Analog Input 6
10 F 0.1 F
47 F * * 2.2nF
RL
2.2nF
Note 3: The value of RL is dictated by the microphone carteridge.
* Capacitors must be C0G or equivalent
Figure 12. Typical Connection Diagram
28
CS4245
4. APPLICATIONS 4.1 Recommended Power-Up Sequence
1) Hold RESET low until the power supply, MCLK1, MCLK2 (if used), LRCK1 and LRCK2 are stable. In this state, the Control Port is reset to its default settings. 2) Bring RESET high. The device will remain in a low power state with the PDN bit set by default. The control port will be accessible. 3) The desired register settings can be loaded while the PDN bit remains set. 4) Clear the PDN bit to initiate the power-up sequence.
4.2
System Clocking
The CS4245 will operate at sampling frequencies from 4 kHz to 200 kHz. This range is divided into three speed modes as shown in Table 1 below. Mode Sampling Frequency 4-50 kHz 50-100 kHz 100-200 kHz
Single Speed Double Speed Quad Speed
Table 1. Speed Modes The CS4245 has two serial ports which may be operated synchronously or asynchronously. Serial port 1 consists of the SCLK1 and LRCK1 signals and clocks the serial audio output, SDOUT. Serial port 2 consists of the SCLK2 and LRCK2 signals and clocks the serial audio input, SDIN. Each serial port may be independently placed into Single, Double, or Quad Speed mode. The serial ports may also be independently placed into Master or Slave mode.
4.2.1
Synchronous / Asynchronous Mode
By default, the CS4245 operates in synchronous mode with both serial ports synchronous to MCLK1. In this mode, the serial ports may operate at different synchronous rates as set by the ADC_FM and DAC_FM bits, and MCLK2 does not need to be provided (the MCLK2 pin may be left unconnected). If the Asynch bit is set (see "Asynchronous Mode (Bit 0)" on page 43), the CS4245 will operate in asynchronous mode. The serial ports will operate asynchronously with Serial Port 1 clocked from MCLK1 and Serial Port 2 clocked from MCLK2. In this mode, the serial ports may operate at different asynchronous rates.
4.2.2
Master Clock
In asynchronous mode MCLK1/LRCK1 and MCLK2/LRCK2 must maintain an integer ratio. In synchronous mode MCLK1/LRCK1 and MCLK1/LRCK2 must maintain an integer ratio. Some common ratios are shown in Table 2.The LRCK frequency is equal to Fs, the frequency at which audio samples for each channel are clocked into or out of the device. The ADC_FM and DAC_FM bits and the MCLK Freq bits (see page 42) configure the device to generate the proper clocks in Master Mode and receive the proper clocks in Slave Mode. Table 2 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies.
29
CS4245
LRCK (kHz) 32 44.1 48 64 88.2 96 128 176.4 192 Mode
MCLK (MHz) 64x 8.1920 11.2896 12.2880 96x 12.2880 16.9344 18.4320 128x 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 QSM Table 2. Common Clock Frequencies 192x 12.2880 16.9344 18.4320 24.5760 33.8680 36.8640 256x 8.1920 11.2896 12.2880 16.3840 22.5792 24.5760 32.7680 45.1584 49.1520 384x 12.2880 16.9344 18.4320 24.5760 33.8680 36.8640 DSM 512x 16.3840 22.5792 24.5760 32.7680 45.1584 49.1520 768x 24.5760 33.8680 36.8640 SSM 1024x 32.7680 45.1584 49.1520 -
4.2.3
Master Mode
As a clock master, LRCK and SCLK will operate as outputs. The two serial ports may be independently placed into Master or Slave mode. Each LRCK and SCLK is internally derived from its respective MCLK with LRCK equal to Fs and SCLK equal to 64 x Fs as shown in Figure 13.
MCLK1 Freq Bits /256 /1 /1.5 MCLK1 /2 /3 /4 000 001 010 011 100 /1 MCLK2 Freq Bits ASynch Bit /256 /1 /1.5 MCLK2 /2 /3 /4 000 001 0 010 1 011 100 /1 10 DAC_FM Bits /4 /2 00 01 SCLK2 /128 /64 00 01 10 LRCK2 10 /128 /64 ADC_FM Bits /4 /2 00 01 SCLK1 00 01 10 LRCK1
Figure 13. Master Mode Clocking
4.2.4
Slave Mode
In Slave mode, SCLK and LRCK operate as inputs. Each serial port may be independently placed into Slave mode. The Left/Right clock signal must be equal to the sample rate, Fs. If operating in asynchronous mode, LRCK1 must be synchronously derived from MCLK1 and LRCK2 must be synchronously derived from MCLK2. If operating in synchronous mode, LRCK1, and LRCK2 must be synchronously derived from MCLK1. For more information on synchronous and asynchronous modes, see "Synchronous / Asynchronous Mode" on page 29.
30
CS4245
For each serial port, the serial bit clock must be equal to 128x, 64x, 48x or 32x Fs depending on the desired speed mode. If operating in asynchronous mode, the serial bit clock SCLK1 must be synchronously derived from MCLK1 and SCLK2 must be synchronously derived from MCLK2. If operating in synchronous mode, SCLK1, and SCLK2 must be synchronously derived from MCLK1. Refer to Table 3 for required serial bit clock to Left/Right clock ratios. Single Speed SCLK/LRCK Ratio 32x, 48x, 64x, 128x Double Speed 32x, 48x, 64x Quad Speed 32x, 48x, 64x
Table 3. Slave Mode Serial Bit Clock Ratios
4.3
High Pass Filter and DC Offset Calibration
When using operational amplifiers in the input circuitry driving the CS4245, a small DC offset may be driven into the A/D converter. The CS4245 includes a high pass filter after the decimator to remove any DC offset which could result in recording a DC level, possibly yielding clicks when switching between devices in a multichannel system. The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the HPFFreeze bit (see page 42) is set during normal operation, the current value of the DC offset for the each channel is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system DC offset calibration by: 1) Running the CS4245 with the high pass filter enabled until the filter settles. See the ADC Digital Filter Characteristics section for filter settling time. 2) Disabling the high pass filter and freezing the stored DC offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration point and the CS4245.
4.4
Analog Input Multiplexer, PGA, and Mic Gain
The CS4245 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA). The input multiplexer can select one of 6 possible stereo analog input sources and route it to the PGA. Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing them to be used for microphone level signals without the need for any external gain. The PGA stage provides 12 dB of gain or attenuation in 0.5 dB steps. Figure 14 shows the architecture of the input multiplexer, PGA, and mic gain stages.
AIN1A AIN2A AIN3A AIN4A/MICIN1 MUX
+32 dB
PGA
Out to ADC Channel A
AIN5A AIN6A Analog Input Selection Bits AIN1B AIN2B AIN3B AIN4B/MICIN2 MUX
+32 dB
Channel A PGA Gain Bits
Channel B PGA Gain Bits
PGA
Out to ADC Channel B
AIN5B AIN6B
Figure 14. Analog Input Architecture
The "Analog Input Selection (Bits 2:0)" section on page 45 outlines the bit settings necessary to control the input multiplexer and mic gain. "Channel A PGA Control - Address 07h" on page 43 and "Channel B PGA Control - Ad31
CS4245
dress 08h" on page 44 outlines the register settings necessary to control the PGA. By default, line level input 1 is selected, and the PGA is set to 0 dB.
4.5
Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals within the stopband of the filter. However, there is no rejection for input signals which are (n x 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient (such as general purpose ceramics) must be avoided since these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
4.6
Output Connections
The CS4245 DAC's implement a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is shown in the "DAC Filter Plots" section beginning on page 50. The recommended external analog circuitry is shown in the Typical Connection Diagram. The CS4245 DAC is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
4.7
Output Transient Control
The CS4245 uses PopguardTM technology to minimize the effects of output transients during power-up and powerdown. This technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.7.1
Power-up
When the device is initially powered-up, the audio outputs AOUTA and AOUTB are clamped to VQ2 which is initially low. After the PDN bit is released (set to `0') the DAC outputs begin to ramp with VQ2 towards the nominal quiescent voltage. This ramp takes approximately 200 ms to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ2, effectively blocking the quiescent DC voltage. Audio output will begin after approximately 2000 sample periods.
4.7.2
Power-down
To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the power. In order to do this either the PDN bit should be set or the device should be reset about 250 ms before removing power. During this time, the voltage on VQ2 and the DAC outputs discharge gradually to GND. If power is removed before this 250 ms time period has passed a transient will occur when the VA supply drops below that of VQ2. There is no minimum time for a power cycle, power may be re-applied at any time.
4.7.3
Serial Interface Clock Changes
When changing the DAC clock ratio or sample rate it is recommended that zero data (or near zero data) be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always be in a zero data state. If non-zero serial audio input is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it's zero data state.
4.8
Auxiliary Analog Output
The CS4245 includes an auxiliary analog output through the AUXOUT pins. These pins can be configured to output the analog input to the ADC as selected with the input MUX and gained or attenuated with the PGA, the analog output of the DAC, or alternatively they may be set to high-impedance. See the "Auxiliary Output Source Select (Bits 6:5)" section on page 43 for information on configuring the auxiliary analog output.
32
CS4245
The auxiliary analog output can source very little current. As current from the AUXOUT pins increases, distortion will increase. For this reason, a high input impedance buffer must be used on the AUXOUT pins to achieve full performance. Refer to the Auxiliary Output Analog Characteristics table on page 18 for acceptable loading conditions.
4.9
De-Emphasis Filter
The CS4245 includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter response is shown in Figure 15. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. Please see section 6.3.4 for de-emphasis control. The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s pre-emphasis equalization as a means of noise reduction. De-emphasis is only available in Single Speed Mode.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 15. De-Emphasis Curve
4.10 Internal Digital Loopback
The CS4245 supports an internal digital loopback mode in which the output of the ADC is routed to the input of the DAC. This mode may be activated by setting the LOOP bit in the Signal Selection register (06h - See page 43). To use this mode, the ADC and DAC must be operating at the same synchronous sample rate. When this bit is set, the status of the DAC_DIF[1:0] bits in register 03h will be disregarded by the CS4245. Any changes made to the DAC_DIF[1:0] bits while the LOOP bit is set will have no impact on operation until the LOOP bit is cleared, at which time the Digital Interface Format of the DAC will operate according to the format selected by the DAC_DIF[1:0] bits. While the LOOP bit is set, data will be present on the SDOUT pin in the format selected by the ADC_DIF bit in register 04h.
4.11 Mute Control
The MUTEC pin becomes active during power-up initialization, reset, muting, if the MCLK2 to LRCK2 ratio is incorrect in asynchronous mode or the MCLK1 to LRCK2 ratio is incorrect in synchronous mode, and during power-down. The MUTEC pin is intended to be used as control for an external mute circuit in order to add off-chip mute capability. Use of the Mute Control function is not mandatory but recommended for designs requiring the absolute minimum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer to achieve idle
33
CS4245
channel noise/signal-to-noise ratios which are only limited by the external mute circuit. The MUTEC pin is an activelow CMOS driver. See Figure 16 below for a suggested active-low mute circuit.
+VEE AC Couple AOUT LPF 47 k -VEE
560
Audio Out
CS4245
+VA MMUN2111LT1 MUTEC 2 k
10 k
-VEE
Figure 16. Suggested Active-Low Mute Circuit
4.12 Control Port Description and Timing
The control port is used to access the registers, allowing the CS4245 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is required. The control port has 2 modes: SPI and IC, with the CS4245 acting as a slave device. SPI mode is selected if there is a high to low transition on the AD0/CS pin, after the RESET pin has been brought high. IC mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit address state.
4.12.1 SPI Mode
In SPI mode, CS is the CS4245 chip select signal, CCLK is the control port bit clock (input into the CS4245 from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 17 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k resistor, if desired. There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK
34
CS4245
will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecutively.
CS
CCLK C H IP ADDRESS C D IN C H IP AD D R ESS LSB b y te n MSB LSB MSB LSB
M AP R/W MSB
DATA
1001111
1001111
R/W
b y te 1
High Impedance
CD OUT
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 17. Control Port Timing in SPI Mode
4.12.2 IC Mode
In IC mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. There is no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the CS4245 is being reset. The signal timings for a read and write cycle are shown in Figure 18 and Figure 19. A Start condition is defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS4245 after a Start condition consists of a 7 bit chip address field and a R/W bit (high for a read, low for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS4245, the chip address field, which is the first byte sent to the CS4245, should match 10011 followed by the settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS4245 after each input byte is read, and is input to the CS4245 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
19
24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
DATA
2 1 0 7 6 1 0 7
DATA +1
6 1 0 7
DATA +n
6 1 0
SDA
START
1
0
0
1
1 AD1 AD0 0
6
5
4
3
ACK
ACK
ACK
ACK STOP
Figure 18. Control Port Timing, IC Write
35
CS4245
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE) MAP BYTE
INCR
STOP
1 0 1
CHIP ADDRESS (READ)
0 0 1 1 AD1 AD0 1
DATA
7 0
DATA +1
7 0
DATA + n
7 0
SDA
1
0
0
1
1 AD1 AD0 0
6
5
4
3
2
ACK START
ACK START
ACK
ACK
NO ACK
STOP
Figure 19. Control Port Timing, IC Read
Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in Figure 19, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition. Send 10011xx0 (chip address & write operation). Receive acknowledge bit. Send MAP byte, auto increment off. Receive acknowledge bit. Send stop condition, aborting write. Send start condition. Send 10011xx1(chip address & read operation). Receive acknowledge bit. Receive byte, contents of selected register. Send acknowledge bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit.
36
CS4245
4.13 Interrupts and Overflow
The CS4245 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin on the host microcontroller. The INT pin may function as either an active high CMOS driver or an active low opendrain driver (see "Active High/Low (Bit 0)" on page 46). When configured as active low open-drain, the INT pin has no active pull-up transistor, allowing it to be used for wired-OR hook-ups with multiple peripherals connected to the microcontroller interrupt input pin. In this configuration, an external pull-up resistor must be placed on the INT pin for proper operation. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See "Interrupt Status - Address 0Dh" on page 46. Each source may be masked off through mask register bits. In addition, each source may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer. The CS4245 also has a dedicated overflow output. The OVFL pin functions as active low open drain and has no active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR of the ADCOverflow and ADCUnderflow conditions available in the Interrupt Status register, however, these conditions do not need to be unmasked for proper operation of the OVFL pin.
4.14
Reset
When RESET is low, the CS4245 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are muted. When RESET is high, the control port becomes operational and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register will then cause the part to leave the low power state and begin operation. The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through the application of power or by setting the RESET pin high. However, the voltage reference will take much longer to reach a final value due to the presence of external capacitance on the FILT1+ and FILT2+ pins. During this voltage reference ramp delay, both SDOUT and DAC outputs will be automatically muted. It is recommended that RESET be activated if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues.
4.15 Synchronization of Multiple Devices
In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure synchronous sampling, the master clocks and left/right clocks must be the same for all of the CS4245's in the system. If only one master clock source is needed, one solution is to place one CS4245 in Master Mode, and slave all of the other CS4245's to the one master. If multiple master clock sources are needed, a possible solution would be to supply all clocks from the same external source and time the CS4245 reset with the inactive edge of master clock. This will ensure that all converters begin sampling on the same clock edge.
4.16 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4245 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 12 shows the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital filter, may be run from the system logic supply (VLS or VLC) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be powered from VD. Power supply decoupling capacitors should be as near to the CS4245 as possible, with the low value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT1+, FILT2+, VQ1 and VQ2 pins in order to avoid unwanted coupling into the modulators. The FILT1+, FILT2+, VQ1 and VQ2 decoupling capacitors, particularly the 0.1 F, must be positioned to minimize the electrical path from FILT1+ and FILT2+ and AGND. The CS4245 evaluation board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the CS4245 digital outputs only to CMOS inputs.
37
CS4245
5. REGISTER QUICK REFERENCE
This table shows the register names and their associated default values. Addr Function 7
PART3 1 02h Power Control 03h DAC Control 1 04h ADC Control 05h MCLK Frequency 06h Signal Selection Freeze 0 0 0 Reserved 0
6
PART2 1 0 0 0 MCLK1 Freq2 0
5
PART1 0 0 0 0 MCLK1 Freq1 0
4
PART0 0 Reserved 0 0 ADC_DIF 0 MCLK1 Freq0 0 Reserved 0 Gain4 0 Gain4 0 PGASoft 1 Vol4 0 Vol4 0 0 Reserved 0 0
3
REV3 0 PDN_MIC 0 Reserved 1 Reserved 0 Reserved 0 Reserved 0 Gain3 0 Gain3 0 PGAZero 1 Vol3 0 Vol3 0 Reserved 0 ADCClkErr 0 0
2
REV2 0 PDN_ADC 0 MuteDAC 0 MuteADC 0 MCLK2 Freq2 0 Reserved 0 Gain2 0 Gain2 0 Sel2 0 Vol2 0 Vol2 0 Reserved 0 DACClkErr 0 0
1
REV1 0 PDN_DAC 0 DeEmph 0 HPFFreeze 0 MCLK2 Freq1 0 LOOP 0 Gain1 0 Gain1 0 Sel1 0 Vol1 0 Vol1 0 Reserved 0 ADCOvfl 0 ADCOvflM 0 ADCOvfl1 0 ADCOvfl0 0
0
REV0 1 PDN 1 DAC_M/S 0 ADC_M/S 0 MCLK2 Freq0 0 ASynch 0 Gain0 0 Gain0 0 Sel0 1 Vol0 0 Vol0 0 Active_H/L 0 ADCUndrfl 0 ADCUndrflM 0 ADCUndrfl1 0 ADCUndrfl0 0
01h Chip ID
Reserved Reserved
DAC_FM1 DAC_FM0 DAC_DIF1 DAC_DIF0 ADC_FM1 ADC_FM0 Reserved
Reserved AOutSel1 AOutSel0 0 1 0 Gain5 0 Gain5 0
07h PGA Ch B Gain Reserved Reserved Control 0 0 08h PGA Ch A Gain Reserved Reserved Control 0 09h Analog Input Control 0Ah DAC Ch A Volume Control 0Bh DAC Ch B Volume Control 0Ch DAC Control 2 0
Reserved Reserved Reserved 0 Vol7 0 Vol7 0 DACSoft 1 0 0 Vol6 0 Vol6 0 1 0 0 0 Vol5 0 Vol5 0 0 0 0
DACZero InvertDAC Reserved
0Dh Interrupt Status Reserved Reserved Reserved 0Eh Interrupt Mask 0Fh Interrupt Mode MSB 10h Interrupt Mode LSB Reserved Reserved Reserved 0
Reserved ADCClkErrM DACClkErrM
Reserved Reserved Reserved 0 0 0
Reserved ADCClkErr1 DACClkErr1 0 0 0
Reserved Reserved Reserved 0 0 0
Reserved ADCClkErr0 DACClkErr0 0 0 0
38
CS4245
6. 6.1 REGISTER DESCRIPTION Chip ID - Register 01h
B6 PART2 B5 PART1 B4 PART0 B3 REV3 B2 REV2 B1 REV1 B0 REV0 B7 PART3
Function:
This register is Read-Only. Bits 7 through 4 are the part number ID which is 1100b (0Ch) and the remaining bits (3 through 0) are for the chip revision.
6.2
Power Control - Address 02h
6 Reserved 5 Reserved 4 Reserved 3 PDN_MIC 2 PDN_ADC 1 PDN_DAC 0 PDN
7 Freeze
6.2.1
Freeze (Bit 7)
Function:
This function allows modifications to be made to certain control port bits without the changes taking effect until the Freeze bit is disabled. To make multiple changes to these bits take effect simultaneously, set the Freeze bit, make all changes, then clear the Freeze bit. The bits affected by the Freeze function are listed in Table 4 below. Table 4. Freeze-able Bits Name MuteDAC MuteADC Gain[5:0] Gain[5:0] Vol[7:0] Vol[7:0] Register 03h 04h 07h 08h 0Ah 0Bh Bit(s) 2 2 5:0 5:0 7:0 7:0
6.2.2
Power Down MIC (Bit 3)
Function:
The microphone preamplifier block will enter a low-power state whenever this bit is set.
6.2.3
Power Down ADC (Bit 2)
Function:
The ADC pair will remain in a reset state whenever this bit is set.
6.2.4
Power Down DAC (Bit 1)
Function:
The DAC pair will remain in a reset state whenever this bit is set.
6.2.5
Power Down Device (Bit 0)
Function:
The device will enter a low-power state whenever this bit is set. The power-down bit is set by default and must be cleared before normal operation can occur. The contents of the control registers are retained when the device is in power-down. 39
CS4245
6.3
7 DAC_FM1
DAC Control - Address 03h
6 DAC_FM0 5 DAC_DIF1 4 DAC_DIF0 3 Reserved 2 MuteDAC 1 DeEmph 0 DAC_M/S
6.3.1
DAC Functional Mode (Bits 7:6)
Function:
Selects the required range of input sample rates. Table 5. Functional Mode Selection DAC_FM1 0 0 1 1 DAC_FM0 0 1 0 1 Mode Single-Speed Mode: 4 to 50 kHz sample rates Double-Speed Mode: 50 to 100 kHz sample rates Quad-Speed Mode: 100 to 200 kHz sample rates Reserved
6.3.2
DAC Digital Interface Format (Bits 5:4)
Function:
The required relationship between LRCK, SCLK and SDIN for the DAC is defined by the DAC Digital Interface Format and the options are detailed in Table 6 and Figures 7-9. Table 6. DAC Digital Interface Formats DAC_DIF1 DAC_DIF0 0 0 0 1 1 1 0 1 Description Left Justified, up to 24-bit data (default) I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data Format 0 1 2 3 Figure 7 8 9 9
6.3.3
Mute DAC (Bit 2)
Function:
The DAC outputs will mute and the MUTEC pin will become active when this bit is set. Though this bit is active high, it should be noted that the MUTEC pin is active low. The common mode voltage on the outputs will be retained when this bit is set. The muting function is effected, similar to attenuation changes, by the DACSoft and DACZero bits in the DAC Control 2 register.
6.3.4
De-Emphasis Control (Bit 1)
Function:
The standard 50/15 s digital de-emphasis filter response, Figure 20, may be implemented for a sample rate of 44.1 kHz when the DeEmph bit is configured as shown in Table 7 below. NOTE: De-emphasis is available only in Single-Speed Mode. Table 7. De-Emphasis Control DeEmph 0 1 Description Disabled (default) 44.1 kHz de-emphasis
40
CS4245
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 20. De-Emphasis Curve
6.3.5
DAC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 2. Setting this bit will select master mode, while clearing this bit will select slave mode.
6.4
7
ADC Control - Address 04h
6 ADC_FM0 5 Reserved 4 ADC_DIF 3 Reserved 2 MuteADC 1 HPFFreeze 0 ADC_M/S
ADC_FM1
6.4.1
ADC Functional Mode (Bits 7:6)
Function:
Selects the required range of output sample rates. Table 8. Functional Mode Selection ADC_FM1 0 0 1 1 ADC_FM0 0 1 0 1 Mode Single-Speed Mode: 4 to 50 kHz sample rates Double-Speed Mode: 50 to 100 kHz sample rates Quad-Speed Mode: 100 to 200 kHz sample rates Reserved
6.4.2
ADC Digital Interface Format (Bit 4)
Function:
The required relationship between LRCK1, SCLK1 and SDOUT is defined by the ADC Digital Interface Format bit. The options are detailed in Table 9 and may be seen in Figure 7 and 8. Table 9. ADC Digital Interface Formats ADC_DIF 0 1 Description Left Justified, up to 24-bit data (default) I2S, up to 24-bit data Format 0 1 Figure 7 8
41
CS4245
6.4.3 Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels will be muted.
6.4.4
ADC High Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter will be disabled.The current DC offset value will be frozen and continue to be subtracted from the conversion result. See "High Pass Filter and DC Offset Calibration" on page 31.
6.4.5
ADC Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for serial audio port 1. Setting this bit will select master mode, while clearing this bit will select slave mode.
6.5
7
MCLK Frequency - Address 05h
6 MCLK1 Freq2 5 MCLK1 Freq1 4 MCLK1 Freq0 3 Reserved 2 MCLK2 Freq2 1 MCLK2 Freq1 0 MCLK2 Freq0
Reserved
6.5.1
Master Clock 1 Frequency (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK1 signal. See Table 10 below for the appropriate settings. Table 10. MCLK1 Frequency MCLK1 Divider /1 / 1.5 /2 /3 /4 Reserved Reserved MCLK1 Freq2 MCLK1 Freq1 MCLK1 Freq0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 x
6.5.2
Master Clock 2 Frequency (Bits 2:0)
Function:
Sets the frequency of the supplied MCLK2 signal. See Table 11 below for the appropriate settings.
42
CS4245
Table 11. MCLK2 Frequency MCLK2 Divider /1 / 1.5 /2 /3 /4 Reserved Reserved MCLK2 Freq2 MCLK2 Freq1 MCLK2 Freq0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 x
6.6
7
Signal Selection - Address 06h
6 AOutSel1 5 AOutSel0 4 Reserved 3 Reserved 2 Reserved 1 LOOP 0 ASynch
Reserved
6.6.1
Auxiliary Output Source Select (Bits 6:5)
Function:
These bits are used to select the analog output source. Please refer to Table 12 below. Table 12. Auxiliary Output Source Selection AOutSel1 0 0 1 1 AOutSel0 0 1 0 1 Auxiliary Output Source High Impedance DAC Output PGA Output Reserved
6.6.2
Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to "Internal Digital Loopback" on page 33.
6.6.3
Asynchronous Mode (Bit 0)
Function:
When this bit is set, the DAC and ADC may be operated at independent an asynchronous sample rates derived from MCLK1 and MCLK2. When this bit is cleared, the DAC and ADC must operate at synchronous sample rates derived from MCLK1.
6.7
Channel A PGA Control - Address 07h
6 Reserved 5 Gain5 4 Gain4 3 Gain3 2 Gain2 1 Gain1 0 Gain0
7 Reserved
6.7.1
Channel A PGA Gain (Bits 5:0)
Function:
See "Channel B PGA Gain (Bits 5:0)" on page 44.
43
CS4245
6.8 Channel B PGA Control - Address 08h
6 Reserved 5 Gain5 4 Gain4 3 Gain3 2 Gain2 1 Gain1 0 Gain0
7 Reserved
6.8.1
Channel B PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to +12 dB in 0.5 dB steps. The gain bits are in two's complement with the Gain0 bit set for a 0.5 dB step. Register settings outside of the 12 dB range are reserved and must not be used. See Table 13 for example settings. Table 13. Example Gain and Attenuation Settings Gain[5:0] 101000 000000 011000 Setting -12 dB 0 dB +12 dB
6.9
ADC Input Control - Address 09h
6 Reserved 5 Reserved 4 PGASoft 3 PGAZero 2 Sel2 1 Sel1 0 Sel0
7 Reserved
6.9.1
PGA Soft Ramp or Zero Cross Enable (Bits 4:3)
Function:
Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 14 on page 45. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 14 on page 45. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 14 on page 45.
44
CS4245
Table 14. PGA Soft Cross or Zero Cross Mode Selection PGASoft 0 0 1 1 PGAZeroCross 0 1 0 1 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled (default)
6.9.2
Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 15 below. Table 15. Analog Input Multiplexer Selection Sel2 0 0 0 0 1 1 1 1 Sel1 0 0 1 1 0 0 1 1 Sel0 0 1 0 1 0 1 0 1 PGA/ADC Input Microphone Level Inputs (+32 dB Gain Enabled) Line Level Input Pair 1 Line Level Input Pair 2 Line Level Input Pair 3 Line Level Input Pair 4 Line Level Input Pair 5 Line Level Input Pair 6 Reserved
6.10 DAC Channel A Volume Control - Address 0Ah
See 6.11 DAC Channel B Volume Control - Address 0Bh
6.11 DAC Channel B Volume Control - Address 0Bh
7 Vol7 6 Vol6 5 Vol5 4 Vol4 3 Vol3 2 Vol2 1 Vol1 0 Vol0
6.11.1 Volume Control (Bits 7:0)
Function:
The digital volume control allows the user to attenuate the signal in 0.5 dB increments from 0 to -127 dB. The Vol0 bit activates a 0.5 dB attenuation when set, and no attenuation when cleared. The Vol[7:1] bits activate attenuation equal to their decimal equivalent (in dB). Example volume settings are decoded as shown in Table Table 16. The volume changes are implemented as dictated by the DACSoft and DACZeroCross bits in the DAC Control 2 register (see section 6.12.1). Table 16. Digital Volume Control Example Settings Binary Code 00000000 00000001 00101000 00101001 11111110 11111111 Volume Setting 0 dB -0.5 dB -20 dB -20.5 dB -127 dB -127.5 dB
45
CS4245
6.12 DAC Control 2 - Address 0Ch
7 DACSoft 6 DACZero 5 InvertDAC 4 Reserved 3 Reserved 2 Reserved 1 Reserved 0 Active_H/L
6.12.1 DAC Soft Ramp or Zero Cross Enable (Bits 7:6)
Function:
Soft Ramp Enable Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods. See Table 17 on page 46. Zero Cross Enable Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 17 on page 46. Soft Ramp and Zero Cross Enable Soft Ramp and Zero Cross Enable dictate that signal level changes, either by attenuation changes or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. See Table 17 on page 46. Table 17. DAC Soft Cross or Zero Cross Mode Selection DACSoft 0 0 1 1 DACZeroCross 0 1 0 1 Mode Changes to affect immediately Zero Cross enabled Soft Ramp enabled Soft Ramp and Zero Cross enabled (default)
6.12.2 Invert DAC Output (Bit 5)
Function:
When this bit is set, the output of the DAC will be inverted.
6.12.3 Active High/Low (Bit 0)
Function:
When this bit is set, the INT pin will function as an active high CMOS driver. When this bit is cleared, the INT pin will function as an active low open drain driver and will require an external pull-up resistor for proper operation.
6.13 Interrupt Status - Address 0Dh
7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 ADCClkErr 2 DACClkErr 1 ADCOvfl 0 ADCUndrfl
For all bits in this register, a `1' means the associated interrupt condition has occurred at least once since the register was last read. A `0' means the associated interrupt condition has NOT occurred 46
CS4245
since the last reading of the register. Status bits that are masked off in the associated mask register will always be `0' in this register. This register defaults to 00h.
6.13.1 ADC Clock Error (Bit 3)
Function:
Indicates the occurrence of an ADC clock error condition.
6.13.2 DAC Clock Error (Bit 2)
Function:
Indicates the occurrence of a DAC clock error condition.
6.13.3 ADC Overflow (Bit 1)
Function:
Indicates the occurrence of an ADC overflow condition.
6.13.4 ADC Underflow (Bit 0)
Function:
Indicates the occurrence of an ADC underflow condition.
6.14 Interrupt Mask - Address 0Eh
7 Reserved 6 Reserved 5 Reserved 4 Reserved 3 ADCClkErrM 2 DACClkErrM 1 ADCOvflM 0 ADCUndrflM
Function:
The bits of this register serve as a mask for the Status sources found in the register "Interrupt Status - Address 0Dh" on page 46. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in the Status register.
6.15 Interrupt Mode MSB - Address 0Fh 6.16 Interrupt Mode LSB - Address 10h
7 Reserved Reserved 6 Reserved Reserved 5 Reserved Reserved 4 Reserved Reserved 3 ADCClkErr1 ADCClkErr0 2 DACClkErr1 DACClkErr0 1 ADCOvfl1 ADCOvfl0 0 ADCUndrfl1 ADCUndrfl0
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT pin remains active during the interrupt condition.
00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved
47
CS4245
7. PARAMETER DEFINITIONS
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels. Total Harmonic Distortion + Noise The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A. Frequency Response A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
Dynamic Range
48
CS4245
8. PACKAGE DIMENSIONS
48L LQFP PACKAGE DRAWING
E E1
D D1
1
e
B A A1
L
MIN --0.002 0.007 0.343 0.272 0.343 0.272 0.016 0.018 0.000 * Nominal pin pitch is 0.50 mm DIM A A1 B D D1 E E1 e* L INCHES NOM MAX MIN 0.055 0.063 --0.004 0.006 0.05 0.009 0.011 0.17 0.354 0.366 8.70 0.28 0.280 6.90 0.354 0.366 8.70 0.28 0.280 6.90 0.020 0.024 0.40 0.24 0.030 0.45 4 7.000 0.00 *Controlling dimension is mm. MILLIMETERS NOM MAX 1.40 1.60 0.10 0.15 0.22 0.27 9.0 BSC 9.30 7.0 BSC 7.10 9.0 BSC 9.30 7.0 BSC 7.10 0.50 BSC 0.60 0.60 0.75 4 7.00 *JEDEC Designation: MS022
9. THERMAL CHARACTERISTICS AND SPECIFICATIONS
Parameters Package Thermal Resistance (Note 31) Allowable Junction Temperature 48-LQFP Symbol JA JC Min Typ 48 15 Max 125 Units C/Watt C/Watt C
Notes: 31. JA is specified according to JEDEC specifications for multi-layer PCBs. 49
CS4245
APPENDIX A: DAC FILTER PLOTS
Figure 21. DAC Single Speed Stopband Rejection
Figure 22. DAC Single Speed Transition Band
Figure 23. DAC Single Speed Transition Band
Figure 24. DAC Single Speed Passband Ripple
Figure 25. DAC Double Speed Stopband Rejection
Figure 26. DAC Double Speed Transition Band
50
CS4245
Figure 27. DAC Double Speed Transition Band
0
0
Figure 28. DAC Double Speed Passband Ripple
-10
-10
-20
-30
-20
-40 Amplitude (dB)
Amplitude (dB) -30
-50
-60
-40
-70
-50
-80
-60
-90
-100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 1
0.35 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.75
Figure 29. DAC Quad Speed Stopband Rejection
0 0.2 -5 0.15 -10 -15 -20 -25 -30 -35 -0.1 -40 -0.15 -45 -0.2 -50 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.1
Figure 30. DAC Quad Speed Transition Band
0.05 Amplitude (dB)
Amplitude (dB)
0
-0.05
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
Figure 31. DAC Quad Speed Transition Band
Figure 32. DAC Quad Speed Passband Ripple
51
CS4245
APPENDIX B: ADC FILTER PLOTS
0 -10 -20 -30 0 -10 -20 -30
Amplitude (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Amplitude (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 33. ADC Single Speed Stopband Rejection
Figure 34. ADC Single Speed Stopband Rejection
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 35. ADC Single Speed Transition Band (Detail)
Figure 36. ADC Single Speed Passband Ripple
0 -10 -20 -30
0 -10 -20 -30
Amplitude (dB)
-80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Amplitude (dB)
-40 -50 -60 -70
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 37. ADC Double Speed Stopband Rejection
Figure 38. ADC Double Speed Stopband Rejection
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CS4245
0 -1 -2
0.10 0.08 0.06
Amplitude (dB)
-3 -4 -5 -6 -7 -8 -9 -10 0.46 0.47 0.48 0.49 0.50 0.51 0.52
Amplitude (dB)
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Frequency (norm alized to Fs)
Frequency (norm alized to Fs)
Figure 39. ADC Double Speed Transition Band (Detail)
0 -10 -20 -30
Figure 40. ADC Double Speed Passband Ripple
0 -10 -20 -30
Amplitude (dB)
-80 -90 -100 -110 -120 -130 -140 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Amplitude (dB) Frequency (norm alized to Fs)
-40 -50 -60 -70
-40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140
0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
Frequency (norm alized to Fs)
Figure 41. ADC Quad Speed Stopband Rejection
Figure 42. ADC Quad Speed Stopband Rejection
0 -1 -2 0.10 0.08 0.06
Amplitude (dB)
-3
Amplitude (dB)
0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
-4 -5 -6 -7 -8 -9 -10 0.10
0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08
Frequency (norm alized to Fs)
-0.10 0.00 0.03 0.05 0.08 0.10 0.13 0.15 0.18 0.20 0.23 0.25 0.28
Frequency (norm alized to Fs)
Figure 43. ADC Quad Speed Transition Band (Detail)
Figure 44. ADC Quad Speed Passband Ripple
53
CS4245
Release A1 PP1
Date May 2004 August 2004
Changes Initial Advance Release. Preliminary Release. - Updated the VA power-down mode supply current specification on page 19. Table 18. Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I2C is a registered trademark of Philips Semiconductor. Purchase of I2C Components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use those components in a standard I2C system.
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